1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming interlayer insulators or inter-metal layers.
2. Description of the Related Art
A semiconductor device using two types of TEOS (tetra ethyl ortho silicate) layers or films as interlayer insulators has heretofore been known. This type of semiconductor device has been formed in accordance with a processing flow shown in FIG. 2, for example.
A metal material such as aluminum or the like is deposited on a semiconductor base 201 (this semiconductor base may be a semiconductor substrate itself or one including a semiconductor substrate and several films or layers formed on the semiconductor substrate). Thereafter, the metal material is patterned to predetermined configurations or shapes by photolithography to thereby form metal traces or interconnections 203. The width between the adjacent metal interconnections 203 is about 1.4 .mu.m.
A P-TEOS film (plasma TEOS film) 205 corresponding to a lower interlayer insulator is next formed to a thickness of about 2000 .ANG. by a CVD method using plasma excitation. A condition for forming the P-TEOS film is represented as shown in FIG. 3. Namely, RF power for exciting plasma is a predetermined value (400W in the present example) during a period from the beginning of formation of the P-TEOS film to the completion of its formation (for about 17 seconds).
An O.sub.3 TEOS (ozone TEOS film) 207 corresponding to an upper interlayer insulator is formed on the P-TEOS film 205 in about 8000 .ANG. by an atmospheric-pressure CVD method.
A condition for forming the O.sub.3 TEOS film 207 is represented as shown in FIG. 4.
However, in the above-described method, the shape of the interlayer insulator between the adjacent metal interconnections 203 becomes steep (large in steplike offset or difference in level and steep in gradient) as illustrated in an enlarged cross-sectional view of FIG. 5. As a result, the coverage of the upper metal interconnection formed on the interlayer insulator becomes worse. Further, since an unnecessary metal interconnection material is easy to remain at each steplike-offset portion (on the interlayer insulator located between the metal interconnections 203) upon the patterning process for forming the upper metal interconnection, its improvement has been desired.